Posters

Authors Title
Vijay Kumar K S, Anushree Bhat and Jagdish Gudda Novel X-tolerant LBIST with asynchronous clock support for optimized test-time
Balajiraja Ravinarayanan, Michael Morgan and Yean Fern Yeoh Accelerating Array Fault Diagnosis using Validated Logical-to-Physical Mapping
Darshal Patel, Pradip Kapure, Praveen Ipe and Imtiaz Ahmed Power efficient modular DFT architecture
Ananth G S, Mahadev G and Sanoop S Power Integrity Simulations to aid ATE Hardware design for Reliability and Reusability
Vishwa Deepika Sripada, Jhansi Komala Nallapati and Satya Kumar Somisetty At-speed Coverage Improvement for Complex AI SoC
Meghana Hampali and Jayagowri R Implementation of secure scan architecture for scan based testing with area optimization
Viral Mehta and Kamya Ahuja On Product Clock Generator- Todays necessity to At-speed testing
Priyanka Joshi, Sreenivasa Rao Vuttaravilli, Tushar Jeevan and Leela Krishna Thota Convergent Glitch detection framework on complex Automotive Designs
Prashanth J V and Shivaranjani S Whitespace reduction to minimize test time in hierarchical SoC designs
Dineshkumar C, Nirmala Devi M and Vaishnavi Sankar Enhanced Reliability for VLSI Circuits through an Isolation Forest based Hardware Trojan Detection Method
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Submissions

Conference

Event Location

Radisson Blu Hotel, Bengaluru Outer Ring Road

Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India

Google Maps Direction: https://goo.gl/maps/nyvHRWcNstifH6TE6