Coming Soon...
Posters
| Title | Authors |
|---|---|
| Wafer Sort Testtime Optimization using ML Model | Vishal Shah, Mithun C A, Sandeep Shetty and Hanumanth Mannur |
| Test Method and Apparatus for Additive Jitter Correction in Mesh based Clock Architectures | Sudheer Anumala, Sri Sakthi Santhanam and Ankita Dhole |
| A Pioneering Methodology for Categorizing Timing Arc Discrepancies | Sravan Kumar Challa, Varsha M, Srinikshith Boga and Leela Krishna Thota |
| Elevating Memory Subsystem Verification: Novel Techniques for Enhanced and Robust Validation | Dharini Subashchandran, Ritesh Desai, Pooja Patel and Vatsal Patel |
| AI/ML driven Test Point Identification for optimal PPA and test coverage | Bharath Nandakumar, Sameer Chillarige, Jella Manju Bhargavi and Jaspreet Singh |
| Maximizing ATE Scan Testing Efficiency across Technology Nodes | Arul Karthick Kumar, Balajayarajan Thankaraj and Karthikeyan Soundararajan |
| Machine Learning Classification of NAND Flash Memory for Higher Reliability | Niranjani Rajagopal and Divya Prasad |
| Realigning Vmax/Vmin DFT tests for Optimum Coverage and Test time Improvements | Mithun C A and Vishal Shah |
| Advancements_in_Boundary_Scan_design_and_verification_for_testing_SKUs_with_reduced_functionality | Shalini Mishra, Kedarnath Salimath, Abdul Aleem Ruch and Rajender Kumar Choppadhandi |
| Performance Comparison of Conventional MBIST and Shared Bus Interface based MBIST | Yogesh Tiwari and Ashishkumar Patel |
| Solving verification challenges for modern DRAM based systems requiring Refresh and Refresh Management compliance | Gruheshkumar Patel, Dharini Subashchandran and Shyam Sharma |
| HSIO AC JTAG Testing Solution for Heterogenous ATE Hardware configurations | Sriram Prasath Sekar |
| Simulation of low voltage devices in industrial networks for Engineering Systems | Jyothi K M, Sachin Raizada and Dhanush Rajavel U |
| Hardware Reconfigurable Auto-Reseeding Pseudorandom Pattern Generator | Nandhu Krishna P B, Ramesh Bhakthavatchalu, Geethu Remadevi Somanathan and Jayakrishnan K R |
| A Spyglass Approach to core wrapping concept | Priyanka Bhatt, Meghana L, Tushar Jeevan, Leela Krishna Thota and Varun Patel |
| Guided RAM Sequential ATPG for Test Time and Test Data Volume Reduction | Nitesh Mishra and Hrithik Sahni |
Conference Location
Radisson Blu Hotel, Bengaluru , India. (Marathahalli, Outer Ring Road)
Address: 90/4 Outer Ring Road, Marathahalli, Bengaluru, 560037, India
Google Maps:
Click here for Direction
To Be Decided (TBD)