10th IEEE INTERNATIONAL TEST CONFERENCE INDIA 2026
JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU
CALL FOR WORKSHOP PROPOSAL (CWP)
TTTC India Workshops on VLSI Test & Design-for-Testability (DFT)
Cycle: 2026–2027
The Test Technology Technical Community (TTTC) India, in collaboration with IEEE International Test Conference India, invites proposals from academic institutions across India to host workshops on VLSI Test and Design-for-Testability (DFT).
These 3-day workshops (2 days theory + 1 day lab) strengthen semiconductor test education, foster industry-academia collaboration, and build skilled talent for India's growing semiconductor ecosystem.
Eligibility Criteria for Host Institutes
- Strong VLSI curriculum (UG/PG)
- Active faculty in VLSI / DFT / testing
- Ongoing research activity preferred
- Auditorium (100–120 capacity)
- Lab with 50–60 Linux systems
- EDA tools availability (optional)
- Ability to attract ~100 participants
Responsibilities of Host Institutes
- Prepare brochure and registration portal
- Provide lunch arrangements
- Accommodation for delegates
- Lab setup with tools
- Assign student volunteers
TTTC India Support
- 3–4 industry expert instructors
- Workshop curriculum
- Travel support for delegates
- Guidance on outreach
Proposal Submission
- Institute overview
- Faculty expertise
- Lab infrastructure
- Accommodation details
- Nearby institute outreach
- Preferred workshop dates
Selection Process
Shortlisted institutes will present their proposal at ITC India 2026 in Bengaluru. Final selection will be based on presentation, infrastructure readiness, and alignment with TTTC goals.
Important Dates
Proposal Deadline
May 31, 2026
Selection Notification
June 15, 2026
Workshop Cycle
Sept 2026 – June 2027
Need Help?
For questions regarding submissions or process, contact:
TTTC-India-Workshop-2026@easychair.org