10th IEEE International Test Conference India 2026
HACKATHON
Date
July 19-21, 2026
Location
Radisson Blu, Marathahalli, Bengaluru
About the Hackathon
The Academia Research Track (ART) committee presents the second edition of hackathon which primarily focuses on bringing together students and faculty from academic institutions to solve industry-scale fundamental research problems in the broad area of semiconductor testing.
The ART committee lists below four domains. As a part of the hackathon, each team must:
- Pick an area from the list provided
- Provide a statement of the problem being addressed
- Define the goal and potential of the research
- Submit a research proposal
The initial project proposal submission is limited to 2-pages and must be submitted by the due date. Feedback will be provided to all the teams by the ART committee to help complete the proposed research.
Important Dates
| Milestone | Tentative Date(s) |
|---|---|
| Last date of filling hackathon registration form | 10th March 2026 |
| Last date of submitting proposals (Each team is supposed to submit their initial thoughts and chosen problem statement. Once Problem Statement is selected, it can NOT be changed) | 5th April 2026 |
| Feedback by ART committee on submitted teams problem statement and definition | 15th-20th April 2026 |
| Last date for Round-1 Solution submission | 31st May 2026 |
| Declaration of Round-1 results (All Round-1 Winners to receive fellowships for attending ITC India-2026 conference) | 10th-15th June 2026 |
| Last date for Round-2 Solution submission | 10th July 2026 |
| Declaration of Round-2 results | During ITC-India 2026 Conference |
Problem Statement Domains
1. Functional Fault Model Development
Modern SoCs integrate complex accelerators and heterogeneous processing blocks where traditional structural fault models (stuck-at, transition, path delay) fail to adequately capture functional failures. Furthermore, with advanced technology nodes and long product lifetimes, many failures occur after deployment due to aging effects, wear-out, radiation, and environmental stress requiring in-field testing. In this challenge, participants are tasked with developing meaningful functional fault models for ATE-based testing and in-field testing. AI-assisted functional fault modeling framework may also be developed/explored that can learn fault behavior from simulation traces, RTL activity, or silicon test data. The objective is to identify and classify functional faults that manifest only under specific workloads, data patterns, or control sequences. Participants must clearly define fault abstraction, and validation strategy, and demonstrate how the proposed model improves fault coverage or diagnostic resolution compared to conventional fault models while remaining test-cost efficient.
2. Fault Models for Emerging Memory Types
Emerging memory technologies such as ReRAM, MRAM, PCM, and FeFET exhibit non-volatile behavior, resistance variability, endurance degradation, and asymmetric read/write characteristics that are not addressed by classical SRAM or DRAM fault models. This challenge requires participants to propose new fault models tailored to one emerging memory technology, capturing both device-level phenomena and array-level behavior. Additionally, aging effects in memory devices can also create problems. The solution should describe fault mechanisms, fault primitives, and their impact on read/write operations, along with suitable test algorithms. Emphasis should be placed on how the proposed fault model enables effective manufacturing test and reliability screening.
3. Test Development for Optical Interconnects
As electrical interconnects reach bandwidth and power limits, on-chip and chip-to-chip optical interconnects are being adopted in high-performance systems. Unlike traditional copper interconnects, optical links introduce unique failure modes such as laser aging, waveguide misalignment, coupling loss, and photodetector sensitivity degradation. Additionally, this shift has become noticeable in both die-to-die connections and rack-to-rack connections (inside datacenters for example). In this challenge, participants must design a test strategy and associated fault model for optical interconnects in one/both of the above scenarios, considering both production test and in-field monitoring. The solution should address how faults are stimulated, observed, and distinguished, and propose different types of metrics to evaluate test effectiveness under realistic process, voltage, temperature, and aging variations.
4. Developing fault modelling techniques for analog testing
Unlike digital circuits, where faults can often be represented using well-defined models such as stuck-at or transition faults, analog faults manifest as subtle deviations in parameters like gain, offset, bandwidth, linearity, or noise due to process variations, aging, and environmental effects. Distinguishing between acceptable process-induced variations and actual manufacturing defects becomes difficult, leading to a high risk of either over-testing (false rejects) or under-testing (test escapes). Additionally, analog circuit behavior is highly dependent on operating conditions and component interactions, making it challenging to define compact, scalable fault models that accurately capture real defect mechanisms while remaining computationally tractable for large-scale production testing. In this challenge, participants must define suitable fault modeling and simulation techniques, taking the illustrations of IPs such as PCIE PHY/USB PHY modules. Participants could also develop a scalable fault grading methodology to calculate analog fault coverage as defined in IEEE 2427 standard using available commercial tools.
Evaluation Plan
Round-1: 100 points
- Problem Understanding & Motivation
- Solution Methodology/Strategy Explanation
- Experimental Validation Methodology
- Overall presentation
Round-2
Technical depth, correctness, validation, and realism of the proposed solution with simulation/modeling results.
Important Guidelines
Team Composition
- Participants must be from academic institutions ONLY.
- Maximum team size is 3 to 4 (including mentors from the institute).
- One leader must be identified from each team.
Hackathon Structure
- The hackathon consists of two rounds.
- The first round is a qualifier for the second round.
Problem Statement Definition
- Each team must define a problem statement from any one of the 4 given areas and submit a document suggesting their initial line of thoughts and the exact problem formulation in a single/double-page document (IEEE conference style double-column) by the due date.
- The ART committee shall provide constructive feedback on this document so that the team members can proceed to developing full-fledged solutions to their chosen problem statements.
Submission Process
Uploading Submissions
- Team leads must upload their submissions by the specified due dates on the provided links. Round-1 submissions must include a detailed report with maximum 12 pages (IEEE style double-column) and supporting simulation files/tool run logs etc.
- Ensure submissions are complete and adhere to the guidelines provided.
- Submission to be made through EasyChair.
Team Coordination
- Maintain clear communication within the team to ensure all tasks are completed on time.
- Regularly check for updates or announcements related to the hackathon on the website.
Contact Information
For any queries, please contact:
binod@iitj.ac.in