10th IEEE INTERNATIONAL TEST CONFERENCE INDIA
2026
JULY 19-21, 2026 | RADISSON BLU, MARATHAHALLI, BENGALURU
INDUSTRY SESSIONS
Nithin Gopinath
Texas Instruments
Built-in Intelligence in Analog-to-Digital Convertors
As modern semiconductor systems demand higher speeds, greater integration, and lower power consumption, ensuring consistent analog performance has become increasingly challenging. This keynote explores the evolution of high-speed ADC testing, from traditional trimming techniques to intelligent digital-assisted correction and real-time background calibration. It highlights how built-in intelligence is transforming analog design and test methodologies, enabling improved performance, reduced test costs, and greater resilience to process, voltage, and temperature variations.
Speaker Biography —Nithin Gopinath is a Senior Member Technical Staff at Texas Instruments, where he has spent over 15 years advancing high-speed data converter technologies. His work in architecting, validating, and optimizing state-of-the-art ADC solutions has contributed to innovations in calibration techniques, performance optimization, and test efficiency across demanding applications including wireless communications, aerospace, defense, and instrumentation.
As Post-Silicon Validation & Test Manager for the High-Speed ADC group, Nithin has developed deep expertise in addressing the challenges of analog performance variability, test cost, and design complexity. His extensive experience with high-speed pipelined ADCs, sigma-delta ADCs, and intelligent calibration methodologies provides him with unique insights into the growing role of built-in intelligence in enabling robust, high-performance analog systems.
Nikhil
Marvell
System Level Test at Hyperscale: Transforming DFT for Data Infrastructure
The rise of AI-driven data infrastructure is redefining the demands placed on modern semiconductor systems. As designs evolve from monolithic SoCs to heterogeneous, chiplet-based architectures featuring advanced packaging, high-bandwidth interfaces, and memory-centric computing, traditional Design-for-Test (DFT) approaches are no longer sufficient. This keynote explores how hyperscale workloads and platform-level integration are driving a shift toward system-level test strategies, highlighting the need for hierarchical, package-aware, and data-driven methodologies to ensure quality, reliability, and scalability in next-generation AI infrastructure.
Speaker Biography —Nikhil is an engineering leader with over two decades of experience in semiconductor design and test, currently serving as Director of Engineering at Marvell, where he leads Design-for-Test initiatives for custom silicon powering next-generation AI infrastructure in hyperscale data centers. Throughout his career at Marvell, Intel, and Qualcomm, he has played a pivotal role in delivering complex SoCs across client, server, mobile, IoT, and automotive markets.
His expertise spans the entire silicon lifecycle, from DFT architecture and verification to post-silicon validation, test development, and ATE bring-up. With deep experience in advanced test methodologies, multi-die systems, and high-performance computing platforms, Nikhil brings valuable insights into how Design-for-Test is evolving to address the challenges of hyperscale AI infrastructure and system-level integration.